Leader: B Lithgow
Clayton Second semester 2005 (Day)
Synopsis: Review of combinational and sequential logic circuits. Combinational logic design. State machine design using state tables and state diagrams. Asynchronous and synchronous design and simulation techniques. Introduction to VHDL and the Xilinx FPG A system design environment.
Assessment: Examination (3 hours): 60% + Assignment and laboratory work: 40%
Contact Hours: 26 lecture hours and 26 laboratory/practice class hours