6 points, SCA Band 2, 0.125 EFTSL
Undergraduate - Unit
Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.
Prof Lindsay Kleeman (Clayton)
M Ooi (Malaysia)
- First semester 2017 (Day)
The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. Students will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation
At the successful completion of this unit you will be able to:
- Describe the fabrication processes used for producing CMOS VLSI circuits.
- Assess the performance of a VLSI layout in terms of speed, power and area.
- Predict and manage the metastable failure rate of crossing clock domains.
- Predict and optimise the delay in multiple paths of a VLSI design.
- Apply pipelining and parallelism to digital designs to improve their performance.
- Design, implement and debug a complex digital design using HDL as part of a team.
- Generate professional documentation for a team design project.
Continuous assessment: 40%
Examination: (3 hours) 60%.
Students are required to achieve at least 45% in the total continuous assessment component (assignments, tests, mid-semester exams, laboratory reports) and at least 45% in the final examination component and an overall mark of 50% to achieve a pass grade in the unit. Students failing to achieve this requirement will be given a maximum of 45% in the unit.
2 hours lectures, 3 hours laboratory/practice classes and 7 hours private study per week
See also Unit timetable information
ECE2061 or TRC2500
ECE3073 or TRC3300
ECE4604, ECE5063, ECE5604